Memory card device including a clock generator

ABSTRACT

Disclosed herein is a card having a controller and a clock control circuit. The controller incorporates a core logic, and the clock control circuit incorporates a PLL. When a card becomes idle to wait for commands, the clock control circuit stops the supply of a clock signal to the core logic. The clock control circuit can operate in two clock control modes. In the first clock control mode, the circuit stops the PLL. In the second clock control mode, the circuit shuts off the clock signal to be supplied from the PLL to the controller.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on Japanese Patent Application No.2000-300466, filed Sep. 29, 2000, the contents of which is incorporatedherein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a memory card device that can be usedin various types of electronic apparatuses. More particularly, theinvention relates to a memory card device that includes a clockgenerator.

2. Description of the Related Art

In recent years, various portable electronic apparatuses have beendeveloped. Among them are personal computers, PDAs, digital cameras,mobile telephones. Memory cards, which are removable memory devices, areused in these portable electronic apparatuses. Two types of memory cardsare known. The first is a PCMCIA card (generally known as “PC card”).The second is a SD (Secure Digital) card that is smaller than the PCMCIAcard.

The SD card incorporates a flash memory. It is small and can yet storeas much data as desired and operate at as high a speed as desired. TheSD card has an improved 9-pin interface. Of the nine pins, four serve totransfer data to the host apparatus. Despite a few interface pins ithas, the SD card can transfer data in sufficient performance.

Recently it is demanded that power consumption be reduced in smallmemory cards typified by SD cards. To reduce power consumption in anelectronic device, the supply of clock signals to the internal corelogic units of the electronic device may be stopped as is known in theart. In a device including a PLL (Phase Locked Loop), more powerconsumption can be reduced by stopping the PLL operation itself than bystopping the supply of clock signals from the PLL to the internal corelogic units.

Once the PLL operation is stopped to set the device into power-savingmode, however, it will take much time to set the device return into thenormal operating mode. This is because the PLL cannot generate stableclock signals for some time after it starts operating again. In otherwords, the internal core logic units cannot operate until the clocksignals become sufficiently stable.

Particularly, a memory card that incorporates a nonvolatile memory suchas a flash EEPROM cannot respond fast, because it takes a relativelylong time to access the nonvolatile memory. To make the matter worse,the internal core logic units will need a long time to restart theiroperations once the PLL provided in the device is stopped to save power.The memory card inevitably responds even more slowly.

BRIEF SUMMARY OF THE INVENTION

An object of the present invention is to provide a memory card devicethat can operate fast and can yet save power sufficiently.

To achieve the object, a memory card device is designed to be removablyinserted in a host apparatus, the memory card device comprises: anonvolatile memory device; a controller configured to execute commandssupplied from the host apparatus, thereby to write data into, and readdata from, the nonvolatile memory; a clock signal generator thatincludes a PLL configured to generate a clock signal to be supplied tothe controller; and a clock control unit configured to operate in afirst clock control mode, wherein the clock control unit stops theoperation of the PLL, if the controller becomes idle while the memorycard device is in a first state in which the memory card device receivesa command concerning an access to the nonvolatile memory device from thehost apparatus, and configured to operate in a second clock controlmode, wherein the clock control unit shuts off the clock signaloutputted from the PLL, if the controller becomes idle while the memorycard device is in a second state in which the memory card device needsnot to receive the command concerning an access to the nonvolatilememory device from the host apparatus.

In the memory card device, the clock control unit stops supplying theclock signal to the controller when the controller becomes idle to waitfor commands. The supply of the clock signal can be stopped in twomodes, i.e., the first clock control mode for stopping the operation ofthe PLL, and the second clock control mode for shutting off the clocksignal outputted from the PLL. The clock control mode is switched, fromthe first to the second, or vice versa, in accordance with whether thecurrent state of the card is a state in which the card device receives acommand concerning an access to the nonvolatile memory device from thehost apparatus.

Additional objects and advantages of the invention will be set forth inthe description which follows, and in part will be obvious from thedescription, or may be learned by practice of the invention. The objectsand advantages of the invention may be realized and obtained by means ofthe instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate embodiment of the invention, andtogether with the general description given above and the detaileddescription of the embodiment given below, serve to explain theprinciples of the invention.

FIG. 1 is a block diagram showing a memory card device according to theembodiment of the present invention;

FIG. 2 is a diagram explaining the clock control operation performed inthe memory card device shown in FIG. 1;

FIG. 3 is a diagram illustrating the relation between the clock controlmode and the status of the memory card device of FIG. 1;

FIG. 4 is a flowchart explaining how the clock control circuit stopsgenerating the clock signal in the memory card device of FIG. 1;

FIG. 5 is a block diagram of the clock control circuit provided in thememory card device of FIG. 1;

FIG. 6 is a timing chart explaining how the clock control circuitoperates while the memory card device remains in S_state;

FIG. 7 is a timing chart explaining how the clock control circuitoperates while the memory card device stays in Q_state; and

FIG. 8 is a timing chart showing how the controller incorporated in thememory card device is repeatedly started and stopped.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of the present invention will be described, with referenceto the accompanying drawings.

FIG. 1 shows a memory card device 11 and an electronic apparatus (hostapparatus) 12. The memory card device 11 is an embodiment of theinvention and used in the electronic apparatus 12. More specifically,the device 11 is an SD (Secure Digital) memory card. Nonetheless, it maybe any other type of a memory card device.

The SD memory card 11 can be inserted into, and removed from, a cardslot made in the host apparatus 12. Note that the host apparatus 12 maybe a personal computer, a PDA, a digital camera, a mobile telephone, orthe like. The host apparatus 12 generates commands, which control thedata communication between the SD memory card 11 and the host apparatus12.

As FIG. 1 shows, the SD memory card 11 incorporates a controller 111 anda memory core 112. The memory core 112 is a non-volatile memory such asa flash EEPROM. The controller 111 performs various command processes,in response to commands supplied from the host apparatus 12. Forexample, it writes data into the memory core 112, reads data from thememory core 12 and performs other operations directed by commands.

The controller 111 comprises an input/output interface 201, MPU 202,memory interface 203, buffer memory 204, ROM 205, control logic units206 and 207, and clock control circuit 208. The unit 206 is provided tocontrol the buffer memory 204, and the unit 207 to control the ROM 205.

The input/output interface 201 receives commands and data from the hostapparatus 12 and transmits data to the host apparatus 12. The datacommunication with the host apparatus 12 is performed through a clockline CLK, a command pin CMD and four data pins DAT3 to DAT0 DAT0, DAT1,DAT2, and CD/DAT3. The transfer of commands from the host apparatus 12to the SD memory card 11 and the transfer of data between the hostapparatus 12 and the SD memory card 11 are effected in synchronizationwith the clock signal CLK supplied from the host apparatus 12 to the SDmemory card 11.

The host apparatus 12 need not always supply the clock signal CLK to theSD memory card 11. It may not supply the clock signal to the SD memorycard 11 while data communication is not need between it and the SDmemory card 11.

The input/output interface 201 operates in synchronization with theclock signal CLK supplied from the host apparatus 12. The interface 201incorporates a state machine register 311, which holds the datarepresenting the state the SD memory card 11 takes at present. (Morecorrectly, the data represents the current state of the controller 111.)The SD memory card 11 may take various states. The state of the card 11transits from one state to another states as its operation proceeds.

The state and operating modes of the SD memory card 11 will bedescribed. The card 11 can operate in the following two modes.

(1) Card Identification Mode

While the SD memory card 11 is operating in this mode, the hostapparatus 12 can identify the attributes of the card 11.

(2) Data Transfer Mode

While the SD memory card 11 is operating in this mode, data can betransferred between the memory card 11 and the host apparatus 12. Thefollowing states are defined for the data transfer mode:

-   -   Stand-by State    -   Transfer State    -   Sending-data state    -   Receive-data state    -   Programming State    -   Disconnect State

The stand-by state is the first state the SD memory card 11 takes whenthe operating mode is switched from the card identification mode to thedata transfer mode. As long as the memory card 11 remains in thestand-by state, the host apparatus 12 can transmit no memory-accesscommands.

Once the SD memory card 11 takes the transfer state, it can receivememory-access commands from the host apparatus 12. In other words, thecard 11 waits for memory-access commands. When the card 11 receives amemory-access command while staying in the transfer state, it transitsto the sending-data state or the receive-data state, depending on thetype of the memory-access command.

A specific command supplied from the host apparatus 12 can achieve thetransition of state, from the stand-by state to the transfer state orvice versa. To make a memory access, the host apparatus 12 must transitthe SD memory card 11 from the stand-by state to the transfer state inorder to accomplish a memory access. The card 11 can receive the commandfor indicating transition to the transfer state, while staying in thestand-by state.

Two ground pins GND are used as ground signal terminals. The hostapparatus 12 supplies ground potential to the SD memory card 11 throughthe ground pins GND. A power signal pin VDD is used as a power signalterminal. The host apparatus 12 supplies power voltage to the SD memorycard 11 through the ground pins VDD.

When the SD memory card 11 receives a data-read command in the transferstate, it transits to the sending-data state. While the card 11 remainsin the sending-data state, data is read from the memory core 112 andtransmitted from the card 11 to the host apparatus 12. Upon transmittingall data to the host apparatus 12, the card 11 returns to the transferstate.

When the SD memory card 11 receives a data-write command in the transferstate, it transits to the receive-data state. While the card 11 isstaying in the receive-data state, the data is transferred from the hostapparatus 12 is accumulated in the buffer memory 204. When the data iscompletely accumulated in the buffer memory 204, the state of the SDmemory card 11 changes, from the receive-data state to the programmingstate.

In the programming state, the data stored in the buffer memory 204 iswritten into the memory core 112. When all the data is written into thememory core 112, the SD memory card 11 transits return to the transferstate.

The SD memory card 11 may wait for commands supplied from the hostapparatus 12 in the stand-by state and the transfer state. In thepresent embodiment, the transfer state and the stand-by state will bereferred to as “Q_state” and “S_state,” respectively. The card 11 mustrespond fast to the host apparatus 12 in the Q_state (transfer state),and need not respond fast thereto in the S_state (stand-by state). TheQ_state and the S_state will be explained with reference to FIG. 3.

When the SD memory card 11 (more correctly, the controller 111) becomesidle to wait for commands, it may be stayed in the stand-by state (orSTBY in FIG. 3), or the transfer state (or TRN in FIG. 3). In thepresent embodiment, if the SD memory card 11 becomes idle while it isthe stand-by state (STBY), a first clock control operation is performedin order to achieve lower power consumption, if the SD memory card 11becomes idle while it is the transfer state (TRN), a second clock stopcontrol operation is performed in order to achieve faster clock restart,but at high power consumption.

Referring back to FIG. 1, the components of the controller 111 will bedescribed.

The MPU 202 is a processor that controls the other components of the SDmemory card 11. The MPU 202 executes various commands in accordance withthe program stored in the ROM 202. The memory interface 203 controlsaccesses to the memory core 112. In other words, the interface 203writes data into, read data from, and erase data in, the memory core 112under the control of the MPU 202. The buffer memory 204 is used mainlyas a posted buffer for storing the write data supplied from the hostapparatus 12, which is to be written into the memory core 112.

To program most nonvolatile memories, a representative of which is aflash EEPROM, data must be erased in units of blocks, and new data mustbe written in units of blocks. Inevitably it takes a long time torewrite data in nonvolatile memories. The SD memory card 11 of thisembodiment supplies a signal to the host apparatus 12 when the buffermemory 204 finishes storing the data supplied from the host apparatus12, thus informing the apparatus 12 that the data-write command has beenexecuted. Then, the controller 111 erases data in, and writes data into,the memory core 112 (i.e., flash EEPROM).

The host apparatus 12 may stop supplying the clock signal CLK to the SDmemory card 11, upon receiving the signal informing the completion ofcommand execution. Nonetheless, the card 111 keeps operating, becausethe clock control circuit 208 generates an internal clock signal CLK1.

As indicated earlier, the input/output interface 201 operates insynchronization with the clock signal CLK supplied from the hostapparatus 12. On the other hand, the core logic units provided in thecontroller 111 (i.e., the MPU 202, memory interface 203 and controllogic units (I/F)206 and 207) operates in synchronization with theinternal clock signal CLK1 generated by the clock control circuit 208.

The clock control circuit 208 is a clock-generating circuit having a PLL(phase locked loop). The PLL multiplies the frequency of the sourceclock signal generated by the internal oscillator. The multiplied sourceclock signal is the internal clock signal CLK1. The clock control signal208 is controlled by the clock control signals Q_OFF, S_OFF, CLK_ON, allgenerated in the controller 111.

The clock control signal Q_OFF causes the clock control circuit 208 tostop outputting the internal clock signal CLK1. The clock control signalQ_OFF is used in Q_state. When the clock control circuit 208 receivesthe signal Q_OFF, it stops outputting the internal clock signal CLK1,though the PLL keeps operating. The clock control signal S_OFF causesthe clock control circuit 208 to stop PLL operation. The clock controlsignal S_OFF is used in S_state. When the clock control circuit 208receives the signal S_OFF, it stops PLL operation; thereby the internalclock signal CLK1 is stopped. The clock control signal CLK_ON causes theclock control circuit 208 to start supplying the internal clock signalCLK1 again.

The scheme of clock control will be described, with reference to FIG. 2.

As FIG. 2 shows, the clock control circuit 208 comprises an oscillator(OSC) 401, a PLL 402 and an output circuit 403. The PLL 402 comprises aphase comparator, a low-pass filter, a VCO (Voltage-ControlledOscillator) and a frequency demultiplier. When the clock control circuit208 receives the clock control signal Q_OFF, the output circuit 403 isturned off, whereby the clock control circuit 208 stops outputting theclock signal CLK1. In this case, neither the oscillator 401 nor the PLL402 is stopped. When the clock control circuit 208 receives the clockcontrol signal S_OFF, the oscillator 401, the PLL 402 and the outputcircuit 403 are stopped.

The signal Q_OFF is input to the clock control circuit 208 through atwo-input AND gate G1. The AND gate G1 receives at its first inputterminal the transfer bit (TRAN) of the state machine register 311. Thetransfer bit (TRAN), which is used as Q-state signal, remains at value“1” while the SD memory card 11 stays in the transfer state. The ANDgate G1 receives at its second input terminal an output signal of aclock-stop instruction generating circuit 314. The instructiongenerating circuit 314 generates a pulse signal that remains at “1”while the clock-stop instruction bit CLK_STP having logic value “1” isset at a prescribed position in the register 312 that is provided in theMPU 202.

The MPU 202 sets the clock-stop instruction bit CLK_STP at logic value“1” when the MPU 202 becomes idle to wait for commands. The MPU 202assumes the idling state upon executing all commands (including internaloperations). That is, as shown in FIG. 4, the MPU 202 gets a command CMDfrom the input/output interface 201 when it receives an interruptionsignal INT from the host apparatus 12 (Step S101). This is becauseinterruption signal INT shows that the host apparatus 12 has suppliedthe command CMD to the SD memory card 11. Then, the MPU 202 performs theoperation designated by the command CMD it has acquired (Step S102).Upon finishing the operation, the MPU 202 set the clock-stop instructionbit CLK_STP having logic value “1” in the register 312 unless it hasreceived any new command (Step S103).

The signal S_OFF is input to the clock control circuit 208 through atwo-input AND gate G2. The AND gate G2 receives at its first inputterminal the stand-by state bit (STBY) of the state machine register311. The stand-by state bit (STBY) is set at “1” while the SD memorycard 11 remains in the stand-by state. The AND gate G2 receives at itssecond input terminal an output signal CLK_STP of the clock-stopinstruction generating circuit 314.

The signal CLK_ON is generated by a CLK_ON-generating circuit 313. Thecircuit 313 generates the signal CLK_ON when it is triggered by theinterruption signal INT the input/output interface 201 has generatedupon receipt of a command from the host apparatus 12. The signal CLK_ONcause the clock control circuit 208 to start generating the clock signalCLK1.

FIG. 5 shows the clock control circuit 208 in detail.

As shown in FIG. 5, the clock control circuit 208 comprises an RSflip-flop 501, an oscillator 502, a PLL 503, a driver 504, an inverter(INV) 505, a counter 506, an AND gate 507, and an RS flip-flop 508. Theoscillator 502, PLL 503 and driver 504 correspond to the oscillator 401,PLL 402 and output circuit 403, respectively, which are shown in FIG. 2.The system core 601 shown in FIG. 5 represents all circuits that aredriven by the clock signal CLK1.

How the clock control circuit 208 shown in FIG. 5 performs its functionwill be explained, with reference to the timing charts of FIGS. 6 and 7.

FIG. 6 illustrates how the clock control is effected while the SD memorycard 11 remains in the S_state. The Q output of the RS flip-flop 501stay at “1” until the signal S_OFF is input to the clock control circuit208. The Q output of the RS flip-flop 508 stay at “1” until the signalS_OFF is input to the clock control circuit 208. Hence, the oscillator502 and the PLL 503 are on. The oscillator 502 outputs a source clocksignal S_CLK, which is supplied to the PLL 503. The PLL 502 multipliesthe clock signal S_CLK, thereby generating a clock signal PLL_CLK. Thecounter 506 counts the pulses of the clock signal S_CLK for apredetermined time (WAIT TIME in FIG. 6) the PLL 504 requires until itstarts a stable operation. The counter 506 outputs a signal “1” uponcounting a prescribed number of the pulses after it has been reset.Hence, the driver-on signal DR_ON output from the AND gate 507 remainsat “1” until the signal S_OFF is input to the clock control circuit 208.Thus, before the signal S_OFF is input, the driver 504 supplies theclock signal PLL_CLK, or the clock signal CLK1, to the system core 601.

When the MPU 202 become idle to wait for commands in the S_state (STBY),the signal S_OFF is generated in the controller 111. Therefore, the Qoutput of the RS flip-flop 501 becomes “0,” stopping both the oscillator502 and the PLL 503. The clock control circuit 208 no longer outputs aclock signal PLL_CLK, or the clock signal CLK1. The inverter 503 invertsthe Q output, resetting the counter 506. The counter 506 outputs asignal “0”. The driver 504 is therefore stopped.

The host apparatus 12 may generates a command in this condition. If so,a signal CLK_ON is generated and supplied to the clock control circuit208. In the circuit 208, the Q output of the RS flip-flop 501 is set at“1.” Then, the oscillator 502 and the PLL 503 start operating, wherebythe circuit 208 begins to output the clock signal PLL_CLK. Upon lapse ofa predetermined time from the start of the oscillator 502 and PLL 503,the counter 506 outputs “1,” setting the driver-on signal DR_ON at “1.”Thus, the clock signal CLK1 would not be output before the operation ofthe PLL 503 comes stable.

FIG. 7 illustrates how the clock control is effected while the SD memorycard 11 remains in the Q state. The Q output of the RS flip-flop 501 andthe Q output of the RS flip-flop 508 remain at “1” until the Q_OFF isinput to the clock control circuit 208. The oscillator 502 and the PLL503 therefore remain on. The oscillator 502 outputs a clock signalS_CLK, and the PLL 503 outputs a clock signal PLL_CLK obtained bymultiplying the clock signal S_CLK. The driver-on signal DR_ON is heldat “1,” too. The driver 504 therefore supplies the signal PLL_CLK, asclock signal CLK1, to the system core 601.

When the MPU 202 become idle to wait for commands in the Q_state (TRAN),the signal Q_OFF is generated in the controller 111. Therefore, the Qoutput of the RS flip-flop 508 becomes “0,” and the driver-on signalDR_ON supplied from the AND gate 504 becomes “0.” Hence, the driver 504shuts off the signal PLL_CLK. The clock control circuit 208 no longeroutputs the clock signal CLK1. Both the oscillator 502 and the PLL 503keep operating.

The host apparatus 12 may generates a command in this condition. If so,a signal CLK_ON is generated and supplied to the clock control signal208. In the circuit 208, the Q output of the RS flip-flop 508 is set at“1.” The driver-on signal DR_ON is thereby set at “1.” Thus, the clockcontrol circuit 208 immediately outputs the clock signal CLK1 again.

In the present embodiment, two clock control schemes are interchangeablyused, depending on the internal state of the SD memory card 11. In thefirst control scheme, the PLL 503 is stopped. In the second controlscheme, the PLL 503 keeps operating and the clock signal CLK1 is notsupplied to the core logic units.

FIG. 8 illustrates how the controller 111 is repeatedly started andstopped.

HOST COMMAND shows a transition of a signal supplied from the hostapparatus 12 to the SD memory card 11 through the command pin CMD.COMMAND indicates the command itself. COMMAND EXECUTED shows the timewhen the controller 111 executes the command COMMAND.

In the Q state, the supply of the clock signal CLK1 is stopped everytime the controller 111 finishes executing a command, as is illustratedin FIG. 8. When the controller 111 receives another command, the supplyof the clock signal CLK1 is immediately started again and the controller111 immediately starts executing the received command.

In the S state, the PLL 503 is stopped every time the controller 111finishes executing a command. The PLL 503 starts operating when thecontroller 111 receives another command. When the operation of the PLL503 comes stable thereafter, the supply of the clock signal CLK1 isstarted again and the controller 111 starts executing the receivedcommand.

Of the commands supplied from the host apparatus 12, some commands areneed not to be executed by the MPU 302. Upon receipt of these commands,the input/output interface 201 only needs to make a response to the hostapparatus 12. When the input/output interface 201 receives such acommand, the interface 201 generates no interruption signals INT. Inthis case, the control circuit 208 remains to stop the clock signalCLK1.

The clock control circuit according to the present embodimenteffectively works in any type of a card device, such as an I/O card,which incorporates a clock-signal generating circuit.

As described above, the transfer state is Q_state in which the carddevice must respond fast to the host apparatus, and the stand-by stateis S_state in which the card device need not respond fast to theapparatus. The present invention is not limited to an SD memory card.Rather, it may be applied to a card device of any other type. If so, thecard device of any other type must respond fast to the host apparatus,while remaining in the Q_state, and need not respond fast to the hostapparatus, while staying in the S_state. In this case, too, power can besaved, without decreasing the operating efficiency of the circuitsincorporated in the card device.

The circuits incorporated in the card device may operate as efficientlyas desired even if an event takes place to release the card device fromthe idling state. If this is the case, it suffices to operate the clockcontrol circuit in accordance with the clock-stop instruction signalS_OFF. Conversely, the circuits in the card device may fail to operateas efficiently as desired, when an event takes place to release the carddevice from the idling state. In this case, it suffices to operate theclock control circuit in accordance with the clock-stop instructionsignal Q_OFF.

As has been described above, two clock control schemes are automaticallyswitched from one to the other, in accordance with the state in whichthe card device has become idle. The power consumption in the carddevice can be much reduced, without decreasing the operating efficiencyof the circuits incorporated in the card device.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A memory card device capable of being removably inserted in a hostapparatus, said memory card device comprising: a nonvolatile memorydevice; a controller configured to execute commands supplied from thehost apparatus, thereby to write data into, and read data from, thenonvolatile memory device; a clock signal generator including a PLLconfigured to generate a clock signal to be supplied to the controller;and a clock control unit configured to operate in a first clock controlmode, wherein the clock control unit stops the operation of shuts offthe clock signal outputted from the PLL, if the controller becomes idlewhile the memory card device is in a state in which the memory carddevice receives waits to receive a command concerning an access to thenonvolatile memory device from the host apparatus, and configured tooperate in a second clock control mode, wherein the clock control unitshuts off the clock signal outputted from stops the operation of thePLL, if the controller becomes idle while the memory card device is in astate in which the memory card device needs does not wait to receive thecommand concerning an access to the nonvolatile memory device.
 2. Thememory card device according to claim 1, further comprising a clocksupply control unit configured to start the operation of the PLL, when acommand is supplied from the host apparatus to the memory card devicewhile the operation of the PLL is stopped, and to supply the clocksignal to the controller, upon lapse of a predetermined time fromstarting of the operation of the PLL, said predetermined time beingrequired time by the PLL to operate stably.
 3. The memory card deviceaccording to claim 1, wherein the clock signal generator includes anoscillator configured to generate a source clock signal which isinputted to the PLL, and the clock control unit stops both the PLL andthe oscillator in the first clock control mode.
 4. A memory card devicecapable of being removably inserted in a host apparatus, said memorycard device comprising: a nonvolatile memory device; a controllerconfigured to be set in a transfer state to receive a command concerningan access to the nonvolatile memory device and to be set in a stand-bystate to receive a command for transition to the transfer state, andconfigure to access to the nonvolatile memory device in accordance witha command concerning an access to the nonvolatile memory device; a clocksignal generator including a PLL configured to generate a clock signalto be supplied to the controller; and a clock control unit configured tooperate in a first clock control mode to stop the operation of the PLLif the controller starts waiting for commands in the stand-by state, andconfigured to operate in a second clock control mode to shut off theclock signal outputted from the PLL if the controller starts waiting forcommands in the transfer state.
 5. The memory card device according toclaim 4, further comprising a clock supply control unit configured tostart the operation of the PLL, when a command is supplied from the hostapparatus to the memory card device while the operation of the PLL isstopped, and configured to supply the clock signal to the controller,upon lapse of a predetermined time from starting of the operation of thePLL, said predetermined time being time required by the PLL to operatestably.
 6. The memory card device according to claim 4, wherein theclock signal generator includes an oscillator configured to generate asource clock signal which is inputted to the PLL, and the clock controlunit stops both the PLL and the oscillator in the first clock controlmode.
 7. A memory card device capable of being removably inserted in ahost apparatus, said memory card device comprising: a nonvolatile memorydevice; a controller configured to execute commands supplied from thehost apparatus, thereby to write data into, and read data from, thenonvolatile memory; a clock signal generator including a PLL configuredto generate a clock signal to be supplied to the controller; a firstclock stop unit configured to stop the operation of the PLL, in order tostop supplying the clock signal to the controller; a second clock stopunit configured to shut off the clock signal outputted from the PLL, inorder to stop supplying the clock signal to the controller; and acontrol unit configured to activate the first clock stop unit or thesecond clock stop unit when the controller becomes idle to wait forcommands, in accordance with a current state of the memory card device.8. The memory card device according to claim 7, further comprising aclock supply control unit configured to start the operation of the PLL,when a command is supplied from the host apparatus to the memory carddevice while the operation of the PLL is stopped, and to supply theclock signal to the controller, upon lapse of a predetermined time fromstarting of the operation of the PLL, said predetermined time being timerequired by the PLL to operate stably.
 9. The memory card deviceaccording to claim 7, wherein the control unit activates the secondclock stop unit if the controller becomes idle while the memory carddevice is in a state in which the memory card device receives a commandconcerning an access to the nonvolatile memory device from the hostapparatus, and activates the first clock stop unit if the controllerbecomes idle while the memory card device is in a state in which thememory card device needs not to receive the command concerning an accessto the nonvolatile memory device from the host apparatus.
 10. A carddevice capable of being removably inserted in a host apparatus, saidcard device comprising: a core logic configured to operate in accordancewith a command supplied from the host apparatus; a clock signalgenerator including a PLL configured to generate a clock signal to besupplied to the core logic; a first clock stop unit configured to stopthe operation of the PLL, in order to stop supplying the clock signal tothe core logic; a second clock stop unit configured to shut off theclock signal outputted from the PLL, in order to stop supplying theclock signal to the core logic; and a control unit configured toactivate the first clock stop unit or the second clock stop unit whenthe core logic becomes idle to wait for commands, in accordance with acurrent state of the card device.
 11. The card device according to claim10, further comprising a clock supply control unit configured to startthe operation of the PLL, when a command is supplied from the hostapparatus to the card device while the operation of the PLL is stopped,and to supply the clock signal to the core logic, upon lapse of apredetermined time from starting of the operation of the PLL, saidpredetermined time being time required by the PLL to operate stably. 12.A memory card device capable of being removably inserted in a hostapparatus, the memory card device comprising: a nonvolatilesemiconductor memory device; a controller configured to control accessto the nonvolatile semiconductor memory device and including afunctional block; and a clock circuit including a PLL circuit togenerate a clock signal to be supplied to the functional block, whereinthe clock circuit can assume: a) a first state in which the PLL circuitis not operating while the controller is idle; and b) a second state inwhich the clock signal is not supplied to the functional block while thecontroller is idle and the PLL circuit is operating.
 13. The memory carddevice according to claim 12, wherein the clock circuit includes anoutput circuit to supply the clock signal to the functional block and,in the second state, the output circuit does not output the clock signalto the functional block.
 14. The memory card device according to claim12, wherein the clock circuit further includes an oscillator to generatea source clock signal to be supplied to the PLL circuit, and in thefirst state, the oscillator does generate the source clock signal. 15.The memory card device according to claim 12, wherein the functionalblock is an MPU to execute a command supplied from the host apparatus.16. The memory card device according to claim 12, wherein the functionalblock is a memory interface circuit coupled to the nonvolatilesemiconductor memory device.
 17. The memory card device according toclaim 12, wherein the memory card device assumes a card identificationmode and a data transfer mode.
 18. The memory card device according toclaim 17, wherein the memory card device has nine signal terminalsprovided along an edge of the memory card device.
 19. The memory carddevice according to claim 18, wherein the signal terminals include aclock signal terminal and a plurality of data terminals.
 20. The memorycard device according to claim 19, wherein the memory card device is anSD card.
 21. The memory card device according to claim 20, wherein oneof the signal terminals is not aligned with other ones of the signalterminals, and the one of the signal terminals is for receiving datafrom the host.
 22. The memory card device according to claim 21, whereinthe nonvolatile memory device is a flash EEPROM.